It is known that multichip assemblies can be produced by flip-chip bonding of IC chips to an appropriate substrate. See, for instance, K. T. Puttlitz, Journal of Electronic Materials, Vol. 13(1), pages 29-46. Among substrates that can usefully be employed are silicon wafers with a multiplicity of conductor and insulator layers thereon, such as described, for instance, in U.S. Pat. No. 4,675,717, incorporated herein by reference.
In general, producing a multichip assembly of the type that is relevant to this application comprises providing a substrate with an appropriate pattern of solder bumps thereon, placing the chips face-down onto the substrate such that solder bumps on the chips rest atop of the corresponding solder bumps on the substrate, causing a preliminary bond to form between contacting solder bumps (this is frequently referred to as "tacking"), and forming a final bond by reflow of the solder.
In the thus produced assembly the chips are raised above the substrate surface. Exemplarily this "stand-off height" is about 50 .mu.m. The re-flowed solder bumps provide the electrical connections between chips and substrate, as well as serving to mechanically secure the chips to the substrate.
It will be understood by those skilled in the art that a method of producing a multichip assembly of the type discussed comprises one or more testing steps. For instance, the assembly might be tested after the tacking operation, and/or after the reflow operation. If these tests indicate that the assembly meets prescribed specifications then the assembly can be combined in known manner with other components, assemblies, or subsystems into an article of commerce. On the other hand, the assembly itself could form an article of commerce.
If the above referred to testing of the assembly indicates that one or more of the chips are not functioning as intended then one can, at least in principle, simply discard the assembly. However, as the number of chips per assembly increases the need for a repair capability increases. In particular, it becomes economically important to be able to replace one or more defective chips on an assembly without at the same time impairing the quality (including the reliability) of the assembly. The above referred to paper by K. J. Puttlitz describes a replacement technique.
Known replacement techniques generally comprise a "dressing" operation during which the height of solder bumps remaining on the substrate after chip removal is adjusted such that all the solder bumps are again of substantially the same height. This is typically accomplished by wicking away some of the solder. The need for dressing of the substrate arises because prior art methods of removing chips typically do not result in the retention of solder bumps of uniform height on the substrate.
It would clearly be desirable to have available a method of chip removal that typically results in the retention on the substrate of solder bumps that are all of substantially the same height, since this may make it possible to dispense with the dressing operation. This application discloses a method of producing an article that comprises such a chip removal method.